1. Field of the Invention
The invention relates generally to semiconductor devices, and more particularly to a novel transistor and method for creation of the same.
2. Description of the Related Art
As semiconductor devices being scaled to achieve high performance and high density circuits, device lateral dimension become smaller. Dopant cross diffusion between oppositely doped regions along shared gate conductor becomes a severe issue. The cross diffusion varies work function of the gate conductor and hence shifts the threshold voltage (Vt) of transistors. At a circuit level, shifted Vt increases transistor mismatch, resulting in low circuit performance or even circuit failures.
FIG. 1 depicts a prior art FET. The feature characteristic of this prior art FET is the dopant cross diffusion that occurs at the junction 130 of the N and P type doped regions. As depicted in FIG. 1, a larger percentage of N type dopant cross diffusion occurs at the P/N junction 130 closest to the gate electrode region doped with N type dopant ions 120, while a larger percentage of P type dopant cross diffusion occurs at the P/N junction 130 closest to the gate electrode region doped with P type dopant ions 110. As depicted in FIG. 1, a larger overall percentage of dopant cross diffusion occurs near the top portion of the junction 130 than near the bottom portion of the junction 130, mainly because dopants are implanted to the region close to the top surface of the gate conductor.
The prior art FET of FIG. 1 suffers the disadvantage of the requirement of large spacing between N/ and P/FETs in order to prevent the adverse effects of dopant cross diffusion that occurs at the P/N junction 130. Adverse effects of dopant cross diffusion that occurs at the P/N junction 130 includes higher device mismatch. As semiconductor devices shrink, the industry is under increasing pressure to place devices, such as the N/ and P/FETs, at ever decreasing distances relative to each other. In the case of the prior art FET of FIG. 1, however, chip designers are limited because the distance between the N/ and P/FET can be no closer than the area of the dopant cross diffusion, which occurs at the junction 130 of the N and P type doped regions.
FIG. 2 depicts another prior art FET. The feature characteristic of this prior art FET is that the area of dopant cross diffusion shown in FIG. 1, which occurs at the junction 130 of the N and P type doped regions, has been entirely removed. In its place an interconnect layer of conductive material 190 such as tungsten plug or a TiN layer is formed over the spacers 170, the gate electrode region doped with N type dopant ions 120, the gate electrode region doped with P type dopant ions 110, as well as in the space created by removal of the area of dopant cross diffusion shown in FIG. 1.
The prior art FET of FIG. 2 suffers the disadvantages of lowering chip density and increasing the risk of shorting transistor source and drain regions. As the gate is completely removed from the junction 130, it requires the tips of the gate conductors extend over the active region to maintain gate control to the channel region and to prevent source/drain shorting. In current state-of-the-art semiconductor manufacturing technology, the minimum spacing between n and p doped regions are too small to allow the complete removal of the gate material without risking shorting the source/drain region. The prior art may require an increased N/P spacing, which results in lower chip density. The prior art also requires a tungsten plug or TiN layer to be formed over the completely removed gate conductor region to connect n and p doped gate conductors. Similarly, the minimum N/P spacing does not have enough room to allow for the formation of these structures without shorting source/drain of the transistors.
What is needed in the art is an improved N/ and P/junction that reduces dopant cross diffusion without comprising chip density.